1. Technical Field
The present invention relates to a semiconductor device.
2. Related Art
A typical test pattern utilized for an evaluating a process for a semiconductor device will be described. A general view of a layout of a test chip for a general process evaluation is shown in FIG. 8. Maximum values of a horizontal width d1 and a vertical width d2 in a dimension of a test chip are generally defined by employing a maximum field size of a lithographic apparatus. An evaluation pattern is composed of an assembly of evaluation blocks, which are also called as sub chips 803. The dimensions of the sub chips 803 are constant in the interior of the testing block. The reason thereof is that this leads to a fixed arrangement of measuring probes and a constant moving distances thereof in a program for measurement, thereby allowing a sharing of a program and a common use of measurement probes.
Subsequently, an outline of a pattern for evaluating an interconnect-related process will be described in reference to FIG. 9. The pattern for evaluating the interconnect process includes via chains, a pattern for evaluating electro migration (EM), a pattern for measuring a leakage or the like, which are mounted therein. Concerning the via chain, a pattern scaling is generally changed according to the length of the interconnect to be evaluated and the number of vias. A defect density can also be evaluated by utilizing different pattern scales. An evaluation block required for such process evaluation is referred to as test element group (TEG) region 901, and the electrode that a probe for electrical measurement lets come into contact is called electrode pad 902, and an interconnect that couples the TEG region 901 to the electrode pad 902 is referred to as a drawing interconnect 903.
An enlarged view of a region for coupling the TEG region to the electrode pad is illustrated in FIG. 10. FIG. 10 is a plan view, which includes a via chain pattern TEG region 1001 and drawing interconnects 1002, which electrically couples the region 1001 is to the electrode pads. Portions of the drawing interconnects 1002 coupled to via chain pattern TEG region 1001 are formed to have a linewidth that is larger than a linewidth of the interconnect in the region 1001.
In the via chain pattern TEG region 1001, M1 interconnects 1003 and M2 interconnects 1004 are alternately disposed, and these interconnects are mutually coupled by vias 1005. Meanwhile, linewidths d3 of the M1 interconnect 1003 and the M2 interconnect 1004 are 70 nm, which is equivalent to a minimum linewidth in the semiconductor device.
In FIG. 10, turning back M1 interconnects 1006 are provided. Meanwhile, the turning back region has an interconnect data rate of 75% over a minimum normalization area (140 nm×140 nm), which is area of a region 1008 that is composed of four grids having of a square having a side, which is equivalent to a minimum interconnect interval of repeated data. This is because the turning back region stores data in three grids of the above-described four grids.
Subsequently, a general process for forming a multiple-layered interconnect will be described by illustrating an example of a dual-layered interconnect. FIGS. 11A to 11C, FIGS. 12A to 12D, FIGS. 13A to 13D and FIGS. 14A to 14C are cross-sectional views, illustrating the process. These cross-sectional views represent cross sections along dotted line L1 in FIG. 10. First of all, an interlayer insulating film 1102 composed of silicon oxide film or the like is formed on a substrate 1101 via a chemical vapor deposition (CVD) process or the like (FIG. 11A). Elements such as transistors (not shown) are formed in the substrate 1101. Then, a resist 1103 is formed on the interlayer insulating film 1102, and the formed resist 1103 is patterned via a photolithographic process. Further, a pattern of the resist is transferred to the interlayer insulating film 1102 via a dry etch technology to form trenches 1104 for interconnects in desired positions (FIG. 11B). Then, the remained resist 1103 is removed (FIG. 1C).
Then, a resist 1201 is formed on the interlayer insulating film 1102, and the formed resist 1201 is patterned via a photolithographic process (FIG. 12A). Further, a pattern of the resist is transferred to the interlayer insulating film 1102 via a dry etch technology to form trenches 1202 for interconnects in desired positions. Then, the remained resist 1201 is removed (FIG. 12B). Subsequently, a conductor film 1203 such as a copper (Cu) film, an aluminum (Al) film and the like is deposited on the entire surface of the interlayer insulating film 1102 (FIG. 12C). Then, the conductor film 1203 is polished via a chemical mechanical polishing (CMP) process until the interlayer insulating film 1102 is exposed. As a result, an interconnect 1204 having a damascene structure is formed in a desired location of the interlayer insulating film 1102 (FIG. 12D).
Then, a diffusion barrier film 1301 composed of a silicon carbide (SiC) film or the like is formed on the interlayer insulating film 1102 having the interconnect 1204 formed thereon, and then, an interlayer insulating film 1302 composed of a silicon oxide film or the like is formed thereon (FIG. 13A). Subsequently, a resist 1303 is formed on the interlayer insulating film 1302, and the formed resist 1303 is patterned via a photolithographic process (FIG. 13B). Further, a pattern of the resist is transferred to the interlayer insulating film 1302 via a dry etch technology to form trenches 1304 for interconnects in desired positions. Then, the remained resist 1303 is removed. Subsequently, a conductor film 1305 such as a Cu film, an Al film and the like is deposited on the entire surface of the interlayer insulating film 1302 (FIG. 13C). Then, the conductor film 1305 is polished via a CMP process until the interlayer insulating film 1302 is exposed. As a result, vias 1306 are formed in desired locations of the interlayer insulating film 1302 (FIG. 13D).
Then, a diffusion barrier film 1401 composed of a SiC film or the like is formed on the interlayer insulating film 1302 having the vias 1306 formed thereon, and then, an interlayer insulating film 1402 composed of a silicon oxide film or the like is formed thereon (FIG. 14A). Subsequently, a resist is formed on the interlayer insulating film 1402, and the formed resist is patterned via a photolithographic process. Further, a pattern of the resist is transferred to the interlayer insulating film 1402 via a dry etch technology to form trenches 1403 for interconnects in desired positions. Then, the remained resist is removed (FIG. 14B). Subsequently, a conductor film such as a Cu film, an Al film and the like is deposited on the entire surface of the interlayer insulating film 1402. Then, the conductor film is polished via a CMP process until the interlayer insulating film 1402 is exposed. As a result, an interconnect 1404 having a damascene structure is formed in a desired location of the interlayer insulating film 1402 (FIG. 14C).
A structure of a coupling interconnect from a certain isolated block to an electric block in electrically dense blocks is not limited to a TEG drawing interconnect for evaluating the process, and a similar structure is employed for the product. Therefore, a typical conventional product thereof will be described as follows.
FIG. 15 is a plan view, showing an outline of a general logic product. A conventional configuration in a general CPU logic circuit will be described in reference to FIG. 15. This product has four macro-functions, namely an input-output (I/O) block 1501, a random access memory (RAM) block 1502, a logic block 1503 and a phase locked loop (PLL) block 1504.
The I/O block 1501 is an area composed of only interconnects having the linewidth of not smaller than 1 μm. In such area, there is basically no need for a narrower interconnect. Further, this area serves as determining a limitation on an allowable high-current, and maximum values of the linewidth and the via dimension are determined by such area. An interconnect that couples the circuit blocks in the I/O block is composed of two interconnects, namely an interconnect that is coupled to a pad electrode (input interconnect) and an interconnect that is coupled to an internal circuit (output interconnect).
The RAM block 1502 generally includes a memory device of around 1 MB. A priority is given to a miniaturization for the interconnects in such area over an operating speed. Therefore, this area is an area of highest need for narrower interconnects. Relatively few large interconnects are included in this area, and power supply interconnects and ground interconnects are alternately disposed with a pitch of a memory cell size.
The logic block 1503 is a cell, in which higher drive capacity is required, and is also a block, in which power supply interconnects are enhanced. A configuration of this area is basically similar to a configuration of a standard cell of a gate array. The configuration of this area related to the interconnects generally includes enhanced power supply interconnects as compared with that of the RAM, though it is similar to that of RAM. A plurality of couplings between macro circuits are generally included, unlikely in the case of the PLL.
Since stable operations of the power supply, the ground and the capacitor element are prioritized in the PLL block 1504, the PLL block 1504 generally requires second largest linewidth, second only to the I/O region, though the interconnect density therein is lower. The PLL serves as amplifying a signal input from an external transmitter (amplifying a signal to, for example, in 4 times or 5 times of the original), so as to compose clock trees in respective macros. A clock input section and a clock output section in this clock serves as drawing interconnects from the macro circuit. Only two input and output interconnects are basically present in the PLL.
A block coupling structure of two macro circuits in a logic unit will be described in reference to FIG. 16. In FIG. 16, a region between two macro circuits of a first logic region 1601 and a second logic region 1602 is a region 1603. Power supply meshes 1604 and ground meshes 1605 are disposed in the macro. Connections and signal interconnects 1606 serving as a circuit structure factor are disposed between the power supply meshes 1604 and the ground meshes 1605 in the macro. Further, signal interconnects for connecting these macros are drawn. A region for preparing a coupling of the signal interconnects is a region 1607. The macros may be mutually coupled in the same interconnect layer or may be mutually coupled in different interconnect layers.
An enlarged view of the macro is shown in FIG. 17. FIG. 17 shows a logic unit 1701 and a macro coupling region 1702. A portion of the interconnect 1703 has a linewidth that is wider than a linewidth of the interconnect in the macro in the macro coupling region 1702. The interconnect 1703 is coupled to a M2 interconnect 1708 through via 1707 within the macro. The power supply interconnects 1704 and the ground interconnects 1705 are alternately disposed. It is common that the signal interconnects 1706 are disposed between the power supply interconnects 1704 and ground interconnects 1705. Further, it is common that the signal interconnect 1706 is arranged to be in parallel with x direction (transverse direction in the diagram) and with y direction (longitudinal direction in the diagram).
In addition to above, typical prior art documents related to the present invention includes Japanese Patent Laid-Open No. 2004-228111.
However, in the conventional technology, a region of larger data rate causes a varied level of the light exposure in the lithographic operation in the process for manufacturing the semiconductor device, causing a problem of allowing narrower process window. The narrower process window may cause, for example, a break in the end of the macro coupling region, leading to a short circuit.
Optimum level of light exposure in the lithographic process is decreased as the data rate is increased. This is resulted from a flare phenomenon, namely a phenomenon that a blurring is caused in a pattern image by an irregular reflection of a beam through a lens. This phenomenon is characterized that the pattern geometry is changed depending on the data rate. Therefore, in order to inhibiting such phenomenon, it is required to provide a limitation in a range of the available interconnect data rate.